Unmanned Systems Technology 009 | Ocean Aero Submaran S10 | Simulation and testing | Farnborough report | 3W-110xi b2 TS HFE FI | USVs | Data storage | Eurosatory/UGS 2016 report

38 The challenge for the HIL system makers is that the bandwidth of the data in the test system has to be far higher than that of the data in actual use, in order to fully test the performance and include all the diagnostic data. An ECU can have 30,000 types of data that are tagged, for example. That means the specification of the sensors is determined by the bandwidth of the test system rather than the actual resolution of the sensor, as that determines what can be demonstrated as part of the ISO 26262 process. Using off-the-shelf modular hardware such as PXI allows a new radar chip for example to be placed on a PXI card and added to the chassis alongside standard and customised I/O cards to easily provide the functionality. These PXI chassis are connected by high-speed gigabit Ethernet connections, but for higher bandwidth they use reflective memory. This is a high-speed shared memory architecture that enables multiple, separate controllers to share a common set of data. Data is stored locally on each controller, but the data is continuously synchronised across the reflective memory network. The nodes in the network plug into the PXI chassis but are linked by a separate fibre-optic cable to provide a high-speed, deterministic method of data transfer for distributed real-time systems. There is a working group of the IEEE looking at the next generation of deterministic Ethernet networking that would be key part of future HIL systems. Time-sensitive networking would give higher throughput and determinism than now to support higher speed control loops and sensor resolution. A large UAV developer in the US has used this for a beam-forming application with about 60 separate chassis systems sharing data and streaming it to a single location. The increase in performance of the modular HIL chassis and networking is also driving down costs for smaller systems, and leading to HIL on the desktop. These use a smaller chassis with a smaller set of I/Os to allow designers to test out equipment at the desk rather than having to wait for a larger test system to be available. They are based on Compact RIO (cRIO) technology, a cut-down version of PXI with an FPGA card that can be used to run parts of the design before it is available in silicon. With more sensors and higher performance demanded by autonomous systems, the pressure is on the test system provider to deliver higher bandwidth and more availability to allow higher test coverage. One such area is performance testing, August/September 2016 | Unmanned Systems Technology Inserting hardware in the loop to test individual elements of a design in a virtual system is a complex procedure (Courtesy of D-Space)