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33 possible out of the battery system. However, there are many different specifications and form factors for embedded computing boards, determined by different organisations for different markets. Even within a particular specification such as COM-Express (COM-E) or SMARC (Smart Mobility ARChitecture) there can be different, standardised sizes of board. At the same time, chip makers are also producing their own boards with non-standard sizes for particular applications such as small UAVs or driverless cars. Core designs There are CPU, GPU and DSP cores from a number of suppliers that can be combined in many different ways for autonomous systems. A key feature of these cores is support for virtualisation, which allows applications such as operating systems or control systems to each sit in a clearly defined space, either on one CPU or on separate cores. This separation is a key element in demonstrating a safe system, as it means there are areas of the software that cannot be influenced by other, potentially unsafe software. DSPs have traditionally been widely used for vision processing, and these cores are now being optimised for neural networks to add deep learning capabilities so that the sensor system can learn about what it sees. Some DSP cores have also been approved for use in safety-critical applications to the ASIL B safety integrity level, in accordance with the ISO 26262 standard, for vision functions such as free- space detection, traffic sign recognition, pedestrian detection and other neural network-based object detection and recognition applications. These applications are critical for autonomous driving systems, and require ISO certification in order to ensure safe and reliable operation. The certification of a DSP core includes a safety analysis report, safety manual, failure modes effects diagnostic analysis, process audit report, safety features verification report and reference back-end flow. This is all produced by the core designer to be used by the chip maker and then the application and system developer. GPUs are still widely used for graphics and gaming of course, but large arrays of GPU processors are also present in supercomputers and are now being used for neural networks and artificial intelligence for autonomous systems. The GPUs that have been designed for those supercomputers are also intended for use in camera systems for the next generation of driverless cars to detect pedestrians, roads signs and other features, learning from each journey to improve the accuracy of the system. Silicon implementation The latest silicon processing technology uses transistor features as small as 10 nm, which allows billions of transistors to be put on a cost-effective chip but at the expense of a high overall power consumption and complexity. The complexity is managed by using multiple cores, combining four or eight CPU cores with an array of up to 1024 GPU processors, with dedicated processing blocks or with DSP cores. Developing a chip on this type of leading-edge process can cost up to $100 million, so chip makers are taking different, less expensive approaches. Some use silicon manufacturing with larger transistors at 28 nm or above, which is cheaper to design and build, and consumes less power in total. Others use the leading-edge technology for certain high-volume applications and engineering prototypes, then as costs come down over time they move these high-performance devices into production designs. This works for the automotive market, which will take several years for the designs to come to market but it will be in large volumes. Some chip makers take CPU cores and add their own DSP technology and algorithms for applications such as image detection, while others develop all the hardware elements themselves Embedded computing | Focus Unmanned Systems Technology | October/November 2016 A board’s form factor is often determined by power envelope, bandwidth and connector needs as well as the space available This development board from Movidius, now part of Intel, is for embedded vision processing (Courtesy of Movidius)