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7 Platform one Unmanned Systems Technology | June/July Cadence Design Systems has developed the first standalone dedicated processor core for machine learning for chips in driverless cars and UAVs (writes Nick Flaherty). The Vision C5 digital signal processor (DSP) core is a neural network optimised for vision, radar/Lidar and fused-sensor applications that provides high performance of 1 TMAC (multiply- accumulate operations) per second. Current neural network processors use arrays of hundreds of graphics processor units (GPUs), as in Nvidia’s Kepler chip for example. This new core however, developed by Cadence’s Tensilica subsidiary and to be included in a chip design, uses configurable instructions that are optimised to accelerate the execution of convolutional neural networks (CNNs). Using configurable instructions reduces power consumption and increases performance. The core can handle the widely used AlexNet CNN six times faster than the standard GPU benchmark, and nine times faster for other CNNs such as the Inception V3. Having the acceleration at the instruction level gives neural network developers more flexibility in how they implement a network, as the implementation can be changed by changing the code. Previous vision systems in driverless cars and UAVs have required two separate types of vision-optimised computation. The input from the camera has to be enhanced using traditional computational imaging algorithms, then the CNN machine learning algorithms handle object detection and recognition. Existing neural network accelerators use hardware accelerators attached to imaging DSPs, with the neural network code split between running some network layers on the DSP and offloading the CNN layers to the accelerator. Accelerating all the neural network computational layers in the Vision C5 core frees up the main vision DSP to run image enhancement applications independently while the C5 runs the inference tasks. By eliminating data movement between the neural network DSP and the main vision/imaging DSP, the Vision C5 provides a lower-power solution than competing neural network accelerators. It also offers a simple, single-processor programming model for neural networks. “Many system-on-chip developers are in the difficult position of having to select a neural network inference platform today for a product that may not ship for a couple of years or longer,” said Steve Roddy at Cadence. “Not only must neural network processors for ‘always-on’ embedded systems consume low power and be fast on every image, they should also be flexible and future-proof.” The core takes up just 1 mm 2 in the latest silicon process so that it can sit alongside the general-purpose microprocessor core and memory, and still be a cost-effective chip. It uses 1024, 8-bit MACs or 512, 16-bit MACs controlled by 64-bit Very Long Instruction Words, and is designed to link to other cores via the industry-standard iDMA and AXI4 buses. The core comes with the Cadence neural network mapper toolset, which will map any neural network trained with tools such as Caffe or TensorFlow into executable and highly optimised code. This mapper tool uses a set of hand- optimised neural network library functions developed by engineers at Cadence. Chip makers are already working with the core, which is expected to be out in silicon in 2018. Core DSP development Signal processing The Vision C5 digital signal processor core is the first self-contained neural network core for vision, radar/Lidar and fused-sensor processors