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7 Platform one The COM HPC standard is being extended to support functional safety, a key requirement for unmanned systems (writes Nick Flaherty). The standard, developed by the PCIMG group, defines a specification, form factor and pinout for higher performance server modules and client modules that sit on a carrier board to provide more processing performance than single- board computers. Version 1.1 of the COM HPC hardware specification is being considered by the PCIMG group and adds a second standby power pin to handle more power to the processor. “A bigger update is a new set of pins for functional safety [FuSa],” said Christian Eder, the chair of the COM HPC standards group. “We see a lot of demand for this from all sorts of autonomous vehicles where no breakage in the service is allowed,” he said. “The specification is for a dozen pins to replace the reserve pins, so there is compatibility. They are used for the SPI bus where the module is the slave, with status and extra signals to indicate under- or over-voltage, and thermal or power on/off status signals. “This will allow these signals to be delivered by a ‘safety island’ on the module for hardware-supported functional safety. Some Intel chips support FuSa functions, and we will support these,” he said. The first COM HPC server boards in sizes E and D use the Intel Ice Lake Xeon 1700D and 2700D processors. They have up to 20 processor cores with up to 1 Tbyte of memory as well as high-speed PCI Express 4.0 links to vision sensors in autonomous systems, particularly self-driving agricultural and construction equipment, Eder said. One advantage of the COM HPC standard is that the Xeon D chips include hardware support for virtualisation software. This allows deterministic control of the memory cache for more reliable performance. Cache systems store data locally to speed up the operation of the processor, but can have variable latency if the data is not in the cache and has to be fetched from the system memory, which is slower. This can be a problem for a hypervisor, which is software that sits between the processor and the operating system to manage the resources in the chip. “The hypervisor allows us to separate and isolate workloads, and split the hardware into individual partitions with one or more cores, for example combining Windows for HMI, Linux for AI and RTOS for control,” said Michael Reichlin, general manager at RTS, the real-time operating system subsidiary of Congatec. The latest Xeon processors include hardware for cache adaptation in a technique called software SRAM. “Using the cache adaptation to partition the level 3 cache allows each partition to act like a normal cache with a cache allocation,” he said. “We decided to implement the software SRAM with another cache partition, and whatever is loaded into that partition remains in the cache, which maintains the low latency and real-time access, and is used for fast data exchange between cores. You do not have to worry about that, it is handled in the hypervisor.” Computer hardware Spec standard extended The COM HPC standard is being updated to add pins for functional safety Unmanned Systems Technology | April/May 2022