Uncrewed Systems Technology 046

44 Focus | Video systems Software elements for the engine use downloadable configuration code for the programmable data path hardware and state transition controller (STC), and complex algorithms are broken down into smaller ‘contexts’ implemented in the programmable data path hardware. The STC switches between individual operations during processing, and changes the next required operation in a single clock cycle. This provides a configurable data path processing hardware for implementing complex algorithms, which are available in a library of functions. Developers can work with design partners to develop custom libraries. The power efficiency of the AI engine eliminates the need for heat dissipation measures such as heat sinks or cooling fans. The chip has a more traditional HDMI interface than MIPI CSI-2, but that allows it to be package- and pin-compatible with current video encoder devices. This compatibility allows vision system board makers to upgrade easily from one with an encoder chip to one with an encoder plus AI without having to modify the system configuration, keeping migration costs low. Conclusion The demand for higher resolution image sensors, more cameras, AI analysis and remote operation is driving the development of both silicon chips and boards for vision systems. Increasing October/November 2022 | Uncrewed Systems Technology The latest version of the MIPI CSI-2 interface provides low-power operation in UAVs. Introduced in 2005, it has become popular as the interface from an embedded camera to a processor. It is typically implemented for shorter- reach applications on either a D-PHY or C-PHY physical-layer interface, which converts the parallel data from the raw image from the camera sensor into a high-speed serial link, or lane, and deserialises it at the other end, hence SerDes (see main text). D-PHY has been widely adopted for several years, and provides up to 4.5 Gbit/s per lane, although that is set to increase to 9 Gbit/s per lane to support larger image sensors with higher resolution, which requires more bits to be sent. D-PHY is a source synchronous architecture, with a dedicated clock lane and two operating modes for efficiency. One is a high-speed mode with differential signalling for data transfer, the other is a low-power mode with single-ended 1.2 V signalling for control and handshake data. MIPI C-PHY, introduced in 2014, uses a three-wire link and three-phase encoding to provide a total bandwidth of up to 6.0 Gsymbols/s across all three wires. The encoding and mapping of the signals ensure that the three wires are synchronised, which helps with the clock and data recovery on the receiver as the physical layer doesn’t have a dedicated lane for the clock but uses an embedded clock. Because these are both developed under the MIPI Alliance, they can be combined to coexist on one set of pins, reusing most of the circuits except for the line drivers and receivers. That means one PHY block in a chip can operate in either C-PHY mode or D-PHY mode, depending on what the image sensor is using. V4.0 is the first to support transmission of CSI-2 image frames over the low pin-count 3C two- wire interface. CSI-2 can also be implemented over the A-PHY long- reach SerDes interface (up to 15 m) for autonomous vehicles. CSI-2 V4.0 also adds multi-pixel compression for the latest generation of advanced image sensors and RAW28 colour depth to improve the image quality and superior signal-to-noise ratio. An Always-On Sentinel Conduit feature enables a vision signal processor (VSP) in a subsystem to continuously monitor its surrounding environment and then trigger the higher-power, host CPUs only when significant events happen. Typically, the VSP will be either a separate device or integrated with the host CPU within a larger chip. This architecture can be used for vision- based vehicle safety applications, and enables image frames to be economically streamed from an image sensor to a VSP over a low-power MIPI I3C bus. The RAW28 pixel encoding supports the next generation of high dynamic range automotive image sensors for applications such as those required for ADAS and other safety-critical applications. CSI-2 v4.0 is backwards compatible with all previous versions of the MIPI specification. Interface standards A system-on-module for video processing using a Renesas processor (Courtesy of Aries Embedded)