Uncrewed Systems Technology 049 - April/May 2023

2,000 uncrewed engineering jobs… …all in one place www.uncrewedengineeringjobs.com Image sensors | Focus the high image quality offered by the pin photodiode used in CIS sensors. Instead, wafer-level stacking technology can be used to achieve high-resolution EVS functionality without sacrificing CIS performance. The top-layer wafer uses pin photodiode pixels arranged in a 4 x 4 configuration, forming a macro-pixel. Each macro-pixel substitutes one blue- channel CIS pixel for a clear one, which is usually connected to an EVS readout circuit on the middle wafer. The photodiode is connected via a stacked pixel-level connection, giving an EVS pixel pitch of 8.8 µm, and the photocurrent is converted into a log voltage and fed into a filter amplifier that acts as the actual contrast detection circuit. The filter amplifier also uses a programmable high-pass filter characteristic to avoid noise events driven by leakage currents that would otherwise discharge high-impedance nodes, leading to false event triggers. A subsequent comparator stage detects if a contrast change above the programmed threshold has been detected. When an event is detected, an in-pixel latch stores it, and a 4-bit sample is produced from a ‘time-to- digital converter’ (TDC). This provides a faster and more robust readout than an analogue implementation. The readout circuitry of the EVS pixel array is located on the third wafer and connected to the middle wafer by means of through-silicon vias. The CIS pixel array is read by analogue-to-digital converters that are also on the bottomwafer, alongside an event-signal processor (ESP), an image signal processor, a fast MIPI interface and auxiliary functions. Combining the event-driven pixels with the image pixels give the lower power and lower latency. A row-pixel interface detects if at least one pixel in the array has detected an event and subsequently triggers a pulse to request a sample. An asynchronous token-based readout then scans for the first row having an event using skip-logic to jump over rows that don’t have to be read. The skip-logic is implemented hierarchically to reduce the load on driving stages and buffers. If a row is found to have an event, a signal is sent back to the array and the column readout block. Four parallel readout channels, each running at up to 250 MHz, provide a data throughput rate of 1 GEvent/s (GEPS) without having to drive the entire scanner with a 1 GHz clock, reducing the power consumption by a factor of eight. The column readout samples all the information in the selected row and provides a signal to the row’s pixel interface indicating that a new sample pulse can be generated. If all the buffers are occupied, the scan has to be stopped to avoid data loss. That can introduce excess latency though, which is why the in-pixel TDC approach is used. The column readout incorporates similar skip-logic to the row selective scanner. The sensor uses a conventional off-pixel time- stamp assignment, where the scanner can detect in parallel if neighbouring pixels share the same polarity. That means only the outermost pixels need to be encoded, reducing the scan and MIPI interface bandwidths, so that a maximum event rate of 4.6 GEPS is achieved. The ESP processing block provides essential functionality such as region-of- interest control, defect pixel correction, event rate limitation, event encoding and caching for the MIPI interface. It also provides auxiliary functions such as ambient light level sensing (ALS) and activity monitoring (AM). The ALS essentially samples the summed photocurrent of all the event pixels by measuring the local current. An event-rate limiter drops events above predefined, programmable thresholds to avoid false triggers. Up to three activity-based thresholds are supported, and are selected in real time based on the AM block. AI integration For computationally intensive applications such as rolling-shutter correction, deblur or slow motion from video frame interpolation, developers need to use the latest neural processor units (NPUs) built in advanced process nodes such as 3 nm CMOS to give the maximum performance and compatibility with software frameworks, rather than the more mature processes used to make image sensors. Delivering uncrewed and autonomous engineering jobs directly to your door uncrewedengineeringjobs.com 2,000 uncrewed engineering jobs… …all in one place