Uncrewed Systems Technology 049 - April/May 2023

7 Platformone Uncrewed Systems Technology | April/May 2023 meet the computational requirements, certification requirements and SWaP limitations at the same time. Without understanding the behaviour of multi-core processors, systemdevelopers can struggle to guaranteemitigation of all potential failure conditions. This is currently solved by disabling three cores in a four-core system for certification, because the interaction between the cores cannot be sufficiently managed for the certifying authorities. Daedalean’s AI-enhanced situational awareness software provides certifiable ML in safety-critical aerospace applications with a full multi-core system. Careful partitioning of the hardware allows all the software components to be tested independently without interference. While partitioning all resources is not necessary for certification up to DAL-C, Daedalean chooses to conduct partitioning for two reasons – for the potential to upgrade to DAL-B in the future and to simplify the testing process. The Daedalean system runs on Vyper, a lightweight hypervisor developed in- house. For each software component, it determines what it is allowed to execute and when. Vyper’s minimal partitioning hypervisor runs on small code size, typically 1500 lines, making it easier to certify, and runs multiple isolated partitions with each partition statically assigned to one of four physical CPU cores. Memory management is a key issue for such systems, and a two-level paging architecture provides each partition with its own isolated address space, allowing memory buffers to be safely shared between partitions. Daedalean does not need to use an RTOS in its system, because the virtual machine extensions are designed to be lightweight and self-contained without relying on third-party code. That allows the system to operate without the need for insulation from external sources. However, developers using an RTOS or commercial hypervisor can still run Daedalean software, provided that the RTOS supports the 11th Gen Intel Core i7 processor. That allows developer applications to run on the architecture, as Daedalean reserves CPU cores for this purpose. Aviation guidance from the CAST 32A standard and the more recent AMC 20- 193 adopted in Europe recommends – and in some cases mandates – that all available resources are partitioned among applications to ensure predictable execution and prevent competition for access. In the case of a systemwith four cores, Vyper provides robust partitioning of CPU time, cache levels, systemmemory and device access by partitioning the cores into non-interfering time slices. It uses Intel’s Time Coordinated Computing settings in the processor BIOS to make execution more deterministic, and is coupled with VMX Virtual Machine Extensions to create virtual machines that run the partitions. Virtualization for Directed I/O isolates the PCIe devices and assigns them to partitions. Intel’s Resource Director Technology Framework, particularly Cache Allocation Technology, is used to partition the shared Level 3 cache memory. This allows each partition to have its own cache and memory, and the only primitive used is a FIFO for comms, which is set up at compile time. That allows the system to operate without interrupts. Vyper runs a scheduler on each processor to execute software partitions according to a compile time-defined schedule. To simplify certification, there is no dedicated processor for handling partition hypercalls or managing the overall system state. Instead, the schedule on each processor is responsible for all partitions pinned to that processor. Software partitions can run either application logic or driver code; this distinction is transparent to Vyper. The first implementations are supporting pilots in the cockpit with situational awareness but can scale for fully autonomous systems that are certified as safe to carry passengers. A spiking neural network built using memtransistors can help prevent collisions between autonomous vehicles at night (writes Nick Flaherty). Almost half of fatal accidents occur at night. As vehicles become autonomous, the ways of detecting and avoiding these collisions must evolve too, but current systems are often complicated, resource- intensive or work poorly in the dark. Researchers at Penn State University have therefore developed a sensor based on the neural circuitry insects use to avoid an obstacle. Instead of processing an entire image, they processed only one variable: the intensity of a car’s headlights. Without the need for an onboard camera or image sensor, the detection and processing units were combined, making the overall detector smaller and more energy-efficient. The collision detector uses eight photosensitive memtransistors constructed from a layer of molybdenum disulphide (MoS 2 ) organised as a neural network. Each memtransistor has multiple terminals and includes a memory resistor (memristor) element made from MoS 2 that stores the neural network weight and transistor technology. Multiple memristors can be embedded in a single transistor, enabling it to more accurately model a neuron with multiple synaptic connections. The sensor has an area of only 40 µm 2 and uses only a few hundred picojoules of energy — tens of thousands of times less than existing systems. In real-life, night-time scenarios, the detector could sense a potential two-car accident 2-3 seconds before it happened, giving the vehicle enough time to take corrective action. Driverless cars Neural net’s night crashes assistance