7 Platform one Uncrewed Systems Technology | August/September 2024 Scalable chip architectures for self-driving cars will require new, automated design tools, writes Nick Flaherty, French research lab CEA-Leti has shown an architecture that scales from basic cars to self-driving vehicles. However, this requires a new generation of automated tools for design exploration. “Two years ago, we started a feasibility study with a big automotive OEM to define and specify the high-level architecture of E/E architectures, and at that time there were only two solutions: a softwaredefined vehicle (SDV) based on a GPU, and a discrete solution,” said Denis Dutoit, programme manager for advanced computing and chiplets at CEA-Leti. The study came up with an architecture with separate small chips, or chiplets, for functions such as the I/O, a sensor fusion chiplet to handle four cameras, a high-end sensor chiplet for multiple cameras, radar and Lidar, and a high-performance central processor, or compute chiplet, for the AI and path planning. This leads to nine system options, with different chiplets being combined on a substrate, which requires new tools to explore the design space, Dutoit said. “For the next generation of E/E, the systems are grouped by physical location with central compute in a zonal architecture, but this has challenges with scalability. We have seen the gap between low end and high end is 100 TOPS to 1000 TOPS in compute, and 100 Gbit/s to 1000 Gbit/s in memory bandwidth, and then there is the issue of cost,” he said. Dutoit explained: “We started with the definition of the low-end car, starting with an IO chiplet. This is a monolithic die that is also able to handle minimal processing for low-end applications as a fusion chip that can handle cameras and displays. We have defined a computing extension for this chiplet and this is software-defined. “For ADAS, the amount of computing is so huge you need a specific accelerator, so we defined an ADAS chiplet to handle more cameras and more sensors. Now we want to scale to the high end for infotainment with a new IO chiplet and a new compute chiplet. “Instead of designing nine system-ona-chip devices, we have defined three chiplets for five architectures for each segment with four packaging options – two for standalone, low-cost platforms, [and] I/O + Compute and quad ADAS.” Leti previously developed virtual prototypes with its own simulator, VPSim for benchmarking, which has a good trade-off between speed and accuracy, but it is not good enough for the chiplets, Dutoit said. “We are designing a new development flow with automated exploration of the design space, so that from just the parameters with simulation we can propose candidates and extract key performance indicators, and generate binaries to preform the benchmarks.” This McPAT simulator is designed to be used with multicore power and area simulation. Chips Savouring design flexibility with scalable chiplets Chiplet options for autonomous vehicles (Image courtesy of CEA-Leti)
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